ASIC Design Engineer

The Company

Ayar Labs is commercializing breakthroughs in optical communications that will bring 10x improvements to data center communication bandwidths and energy efficiency by building optical systems in high-volume commercial CMOS chips. We are a small team that is motivated by a mission to get optics inside all electronics, replacing electricity with light, and bringing breakthrough improvements in performance and energy efficiency to computing. We will be growing quickly and we expect every member of our team to grow with us and to be comfortable with both hands-on engineering work and with leading a team or project.

General Description

Responsible for design, implementation, and integration of both analog and digital components as part of a complex SoC with both high-speed custom and digital blocks. You will work as a part of a small IC design team in a dynamic startup environment, taking an active role in design reviews, contributing to product definition, proposing and evaluating technical solutions, writing design specifications and test requirement documents, etc. The ideal candidate is a hands-on self-starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

Desired Qualifications

  • 2+ years of work or academic experience in digital ASIC design
  • Proficient in Verilog both for synthesis and verification
  • Proficient in ASIC synthesis tools (Cadence RTL Compiler/Genus or Synopsys Design Compiler)
  • Proficient in ASIC place-and-route tools (Cadence Encounter/Innovus or Synopsys ICC)
  • Proficient in ASIC verification tools (Cadence NCSIM or Synopsys VCS)
  • Proficient in handling digital designs with multiple clocks and clock dividers
  • Has working knowledge of how to integrate custom blocks in a digital flow (LEF, lib, etc.)
  • Has working knowledge of Cadence Virtuoso design environment for manual schematic entry, layout, and simulation
  • Has working knowledge of final design signoff, such as DRC/LVS cleanup
  • Able to assume responsibility for a variety of technical tasks and to work independently
  • Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
  • Knowledge of high-speed SerDes or SerDes components is a plus

To apply, please email your cover letter and CV to, with the subject line: “ASIC Design Engineer Application”