Breaking Optical I/O Standards While Adjusting to the ‘New Normal’

by | Mar 26, 2020

Our world shifted with the growing criticality of Covid-19 … and we at Ayar Labs shifted with it. Early in the month, we made the difficult decision to not attend the Optical Fiber Communications Conference (OFC), but with tireless hours by our technical team to pull together next-gen demonstrations and an announcement of a new investor, Lockheed Martin, we pivoted and decided to share our demos from our office via video conferencing. Not quite as exciting as being on the busy conference floor at OFC, but it served as a good fallback plan. As we now ‘shelter in place’ in California, we are adjusting to this ‘new normal’ of working from home, teleconferencing, moving lab equipment into homes, and connecting in new and different ways.

Despite the adjustments, this week we are excited to share DARPA’s news about our key milestone for the PIPES project. For the first time, we demonstrated a major SOC (an Intel FPGA) communicating via optical I/O out of package using our optical I/O architecture. We’re also sharing a new video that walks through this demonstration, along with our TeraPHY Single Die Package (SDP).

With these demonstrations, we are advancing optical I/O standards by showing that optical chips can be pushed directly into the CPU/GPU/ASIC package, which is the key to building next-generation computer architectures that are fundamentally impossible with today’s technologies. These new architectures will enable systems that dramatically advance the traditional Moore’s Law benefits for core applications in artificial intelligence, supercomputing, disaggregated cloud systems, and communications.

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Figure 1: (Left) TeraPHY chiplet, (Middle Column) SDP and MCP package form factors, (Right Column) SDP and MCP evaluation boards used in demonstrations.

With this demonstration, we achieved a few key milestones:

  1. A 512 Gb/s transmitter (4 macros x 8 wavelengths x 16Gbps) with all 8 optical channels simultaneously locked and transmitting (Figure 2)
  2. A functional multi-chip package with the host SoC (Intel® FPGA) sending data through the FPGA electrical interface into the TeraPHY electrical interface, and TeraPHY transmitting the data (Figure 3)
  3. The FPGA+TeraPHY demonstration used Ayar Labs’ SuperNova Remote Laser Source as the optical power supply (Figure 3)
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Figure 2: Single Die Package demonstration showing an aggregate 512 Gb/s transmitter.
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Figure 3: Multi-Chip Package demonstration powered by SuperNova remote laser source showing live running optical data.

These milestones take a major step forward in showing that microring-based WDM can meet the requirements for next-generation high-performance chip-to-chip I/O. We showed that our microrings remain thermally locked indefinitely (in our case, we tested up to 14 hours with all 8 wavelengths running simultaneously). We measured better than 1e-12 BER with no error floor observed. We demonstrated that the TeraPHY chiplet can operate inside an advanced multi-chip 2.5D SoC package, and we showed that our SuperNova laser source can be used as a remote laser source. All of these together—optical Tx/Rx, SoC-to-chiplet electrical interface, remote laser source, packaging/assembly/fiber attach—complete the list of items needed for a full solution and set the stage for platform and system architects to start incorporating optical I/O into their next-generation designs.

We will be presenting more technical detail about these achievements at conferences throughout this year and in upcoming blog posts. Also, check out Intel’s blog for more information on the Intel® FPGA and the AIB open interface standard. Stay tuned! And be safe in this ‘new normal.’

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