Enabling Optical Interconnects Using the New UCIe Standard

by | May 18, 2022

Introduced in March of this year, the UCIe standard is a new die-to-die interconnect standard for high-bandwidth, low-latency, power-efficient, and cost-effective connectivity between chiplets. It is also the first specification to include an interface that is compatible with optical links. Ayar Labs’ TeraPHY™ optical I/O chiplet, using an Advanced Interface Bus (AIB) interface, is the first optical interconnect to be “UCIe compatible” and poised to deliver on the promise of disaggregated system architectures for the next era of computing.

The Move to New, Disaggregated System Designs

Large compute systems typically use an architecture where compute and memory resources are tightly coupled to maximize performance. Components such as CPUs, GPUs, and memory must be placed closely together when connected electrically via copper interconnects. This hardware density results in cooling and energy issues, while persistent bandwidth bottlenecks limit inter-processor and memory performance. These issues are exacerbated in compute-intensive applications like HPC, AI, and compute-intensive data analytics.

Today, new disaggregated system architectures with optical interconnect are being investigated to decouple a server’s elements — processors, memory, accelerators, and storage — enabling flexible and dynamic resource allocation, or composability, to meet the needs of each particular workload.

“Disaggregated architectures require communication between memory and processors over longer distances. Pooled resources mean memory, GPUs, and CPUs are each on their own shelves for flexibility in mapping specific resources to specific workloads. Optical interconnects allow off-chip signals to traverse long distances,” explained Nhat Nguyen, Ayar Labs’ senior director of solutions architecture.

UCIe—a Solution for Chiplet Inter-Connectivity

Universal Chiplet Interconnect Express (UCIe) is a new die-to-die interconnect standard for high-bandwidth, low-latency, power-efficient, and cost-effective connectivity between chiplets. UCIe was developed because chip designs are running up against the die reticle limit.

Intel Corporation originated UCIe 1.0, and ten members ratified the specification, including AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC. Current standards that compete with UCIe include OpenHBI, Bunch of Wires (BoW), and OIF XSR.

UCIe provides several benefits over other standards, including:

  • The ability to package dies from different sources, including different fabs, designs, and processing and packaging technologies that can interoperate seamlessly in a single system on chip (SoC)
  • A clear scaling roadmap to address the need for higher bandwidth and shoreline density
  • An interface that is built from the ground up to be compatible with optical links
  • UCIe maps PCIe and Computer Express Link (CXL) protocols natively at the board level across all segments of compute

According to Uday Poosarla, head of product at Ayar Labs, “UCIe has significant advantages over other standards, including scalability, interoperability, and flexibility. UCIe is the first standard to incorporate optics into chip-to-chip interconnects. The CW-WDM MSA, another new standard, provides a great framework for the optical connections, complementing the UCIe standard.”

Enabling Optical Interconnects Using the New UCIe Standard

Ayar Labs is focused on bringing optical I/O into the datacenter to remove the “last mile” of copper interconnect and solve the bandwidth density and scaling problem. Ayar Labs was the first to introduce an optical chiplet using Advanced Interface Bus (AIB) as the interface. UCIe is an evolution of the AIB interface, so Ayar Labs’ current AIB-based optical chiplet is compatible with UCIe standards. The Ayar Labs solution includes the TeraPHY™ in-package OIO chiplet and SuperNova™ laser light source, which can be incorporated into a UCIe-compliant chip package. Each TeraPHY chiplet delivers up to two terabits per second of I/O performance, or the equivalent of 64 PCIe Gen5 lanes.

In addition to being a contributing member of the UCIe, Ayar Labs is also a founding member of the CW-WDM MSA, a consortium dedicated to defining and promoting specifications for multi-wavelength advanced integrated optics. This MSA specification compliments UCIe and may help foster cohesion around light sources for integrated optics in the chiplet ecosystem.

To learn more about our UCIe-compatible optical I/O solution, visit ayarlabs.com/teraphy/

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