Ayar Labs has successfully demonstrated the first ultra-dense optical interconnect solution on GLOBALFOUNDRIES’ next...
Resources
Webinar: Disaggregated System Architectures for Next Generation HPC and AI Workloads
As scientific applications and workflows incorporate AI models, new opportunities for innovation in system...
Demonstration of Ayar Labs’ Optical I/O Multi-Chip Package and Single-Die Package solutions
Our longstanding relationship with DARPA has helped us to achieve a first-of-its-kind demonstration where we have...
Paradigm Change: Reinventing HPC Architectures with In-Package Optical I/O
Even with the first exascale systems just around the corner, HPC centers are already wrestling with what technologies...
Investing in our Vision to Make In-Package Optical I/O a Reality
Discover what Ayar Labs has accomplished in the 2nd quarter of 2020, during these unprecedented times. From opening a...
TeraPHY: An O-band WDM Electro-optic Platform for Low Power, Terabit/s Optical I/O
Abstract: We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The...
Ayar Labs: Solving Critical Computing Challenges through Optical I/O
Discover how our optical I/O solution will solve the critical computing challenges of efficiency, density, and distance for next-gen system architectures.
Technical Brief: Optical I/O Chiplets Eliminate Bottlenecks to Unleash Innovation
This technical brief examines the evolution of optical communications in computing systems and the transition to...
Ayar Labs TeraPHY™ MIPO I/O Chiplet: Enhancing state of the art, advanced architectures
More resources from Ayar Labs:
TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O
Abstract: This slide deck was presented by Mark Wade on August 20, 2019. (48 slides) Authors: Ayar Labs - Dr. Mark...
TeraPHY: A High-density Electronic-Photonic Chiplet for Optical I/O from a Multi-Chip Module
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.