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Resources
Demonstration of Ayar Labs’ Optical I/O Multi-Chip Package and Single-Die Package solutions
Our longstanding relationship with DARPA has helped us to achieve a first-of-its-kind demonstration where we have...
Paradigm Change: Reinventing HPC Architectures with In-Package Optical I/O
Even with the first exascale systems just around the corner, HPC centers are already wrestling with what technologies...
TeraPHY: A High-density Electronic-Photonic Chiplet for Optical I/O from a Multi-Chip Module
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.
A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS
The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O.
WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers
In this work, we present WaveLight, a monolithic silicon-photonics platform whereby a low latency reliable deterministic protocol with optical functions are designed directly into an existing high-volume CMOS process.
Ultra-Efficient CMOS Fiber-to-Chip Grating Couplers
Apodized bi-level fiber-to-chip grating couplers, designed using a complex-wavevector band-structure approach, are demonstrated in a commercially available, monolithic SOI CMOS process achieving 92% (−0.36dB) coupling efficiency.
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning
Here, we present a bit-statistical tuner that decouples tracking of optical one and zero-levels to realize non-dc-balanced data transmission, an “eye-max”-locking controller, and self-heating cancellation without need for a high-speed sensing frontend.
Single-chip microprocessor that communicates directly using light
This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip
This proof-of-principle device demonstrates the potential of commercial CMOS microelectronics as an advanced quantum photonics platform with the capability of large volumes and pristine process control, where state-of-the-art high-speed digital circuits could interact with quantum photonic circuits.
75% Efficient Wide Bandwidth Grating Couplers in a 45 nm Microelectronics CMOS Process
In this paper, we demonstrate a highly directional vertical grating coupler with > 70% chip-to-fiber coupling efficiency (CE) and a 78 nm 1- dB bandwidth fabricated in a 45 nm commercially available microelectronics SOI CMOS process.