This technical brief examines the evolution of optical communications in computing systems and the transition to...

This technical brief examines the evolution of optical communications in computing systems and the transition to...
Ayar Labs demonstrates the industry’s first continuous wave, CW-WDM MSA compliant, 8 wavelength, 8 port optical source...
An explosion in demand for more compute capacity for high-performance computing (HPC) and artificial intelligence (AI)...
Discover what Ayar Labs has accomplished in the 2nd quarter of 2020 during these unprecedented times. From opening a...
Abstract: We demonstrate an electro-optic system enabling a direct optical I/O interface in an ASIC package. The...
Discover how our optical I/O solution will solve the critical computing challenges of efficiency, density, and distance for next-gen system architectures.
More resources from Ayar Labs:
Abstract: This slide deck was presented by Mark Wade on August 20, 2019. It explores Ayar Labs' innovative TeraPHY,...
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.
The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O.
In this work, we present WaveLight, a monolithic silicon-photonics platform whereby a low latency reliable deterministic protocol with optical functions are designed directly into an existing high-volume CMOS process.