Abstract: This slide deck was presented by Mark Wade on August 20, 2019. It explores Ayar Labs' innovative TeraPHY,...
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.
In this paper, we demonstrate a highly directional vertical grating coupler with > 70% chip-to-fiber coupling efficiency (CE) and a 78 nm 1- dB bandwidth fabricated in a 45 nm commercially available microelectronics SOI CMOS process.
A silicon-photonic link is monolithically-integrated in a bulk CMOS process for the first time.
Based on a novel, “spoked-ring” active microcavity, we demonstrate optical modulators in an unmodified 45nm SOI CMOS process at 5Gbps with <5fJ/bit energy consumption; and filters with record thermal tuning efficiency of 2µW/GHz.