Collaborations & Alliances

The industry’s move to chiplets promises increased performance, reduced power, size, and weight, and is key to enabling Moore’s Law when used in heterogeneous integration. Chiplets also require significant advances in system design, as well as active ecosystem engagement, healthy commercial alliances, and strict adherence to industry design standards from all vendors involved in order to avoid exclusions, limitations, and single-source designs.

Ayar Labs maintains a commercial business model that ensures broad industry ecosystem collaboration to ensure ready adoption of our TeraPHY products, which are poised to become the industry’s de facto standard for state-of-the-art Monolithic In-Package Optical I/O (MIPO I/O) chiplets. We actively participate in, adhere to, and/or collaborate with the following industry alliances and industry standards bodies and specifications:

  • Advanced Interface Bus (AIB) An open, royalty-free interconnect standard for chiplet architectures.
  • Compute Express Link (CXL) – An industry consortium specification designed to enable any-to-any connectivity in high-performance datacenter computing. The consortium is an open interconnect CPU-to-device and CPU-to-memory ecosystem designed to remove the bottlenecks between general-purpose and accelerated processing architectures.
  • DARPA’s Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) A program designed to develop the design tools and integration standards required to develop modular electronic systems.
  • DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program this program seeks to emplace integrated optical transceiver capabilities into cutting-edge multi-chip modules for performance well beyond currently available solutions through novel optical I/O approaches and advanced optical packaging and switching technologies.

  • Intel Corporation’s Embedded Die Interconnect Bridge (EMIB) – A design approach where a small embedded silicon connection allows a host chip and a secondary chiplet to connect together with high bandwidth and small distances. This technology is currently utilized in Intel FPGAs, connecting the FPGA to memory or transceivers or third-party IP.
  • NSTXL – The National Security Technology Accelerator (NSTXL) prospects and develops innovative technology from across the broad commercial and non-traditional defense marketplace, ensuring the development of better, cheaper, and faster defense capabilities that enhance mission and support the Warfighter.

Intel’s Vice President of Strategy & Innovation, Vince Hu, speaks to the explosion of data volume in cloud, telecom, and HPC and the need for Ayar Labs’ optical I/O solutions to solve the I/O bottleneckettings.

 

Pin It on Pinterest

Share This