Hewlett Packard Enterprise and Ayar Labs have teamed up to develop next-generation data center architectures and networking with Optical I/O. The strategic collaboration focuses on Ayar Labs’ development of high speed, high density, low power optical-based interconnects to target future generations of HPE Slingshot, the industry’s only high performance Ethernet fabric specifically designed for high performance computing (HPC) and artificial intelligence (AI) solutions.
Intel and Ayar Labs are working together on multiple fronts to drive next-generation system architectures. One area is the DARPA PIPES program. We replaced the traditional electrical I/O of a state-of-the-art FPGA with efficient optical signaling interfaces to achieve 5.12 Tbps performance. We combined an Intel Stratix 10 FPGA core with five Ayar Labs TeraPHY™ optical I/O chiplets, creating a multi-chip module with in-package optics to substantially improve interconnect reach, efficiency, and latency. We expect this work to impact numerous applications including HPC, AI, large-scale simulation, and DOD-specific capabilities such as phased array radar.
Lockheed Martin is partnering with Ayar Labs in developing multi-chip package (MCP) solutions that place high-density, high-efficiency optical I/O chiplets in the same microelectronics package as the RF processing devices. The development and integration of Ayar Labs’ TeraPHY™ optical I/O chiplets and SuperNova™ light source represent a faster, more efficient, and more reliable transfer of data throughout the platform. This is important for next-generation architectures that will use phased array apertures to connect systems and people to make smarter, faster decisions.
Ayar Labs and NVIDIA are developing groundbreaking AI infrastructure based on optical I/O technology to meet future demands of AI and HPC workloads. The collaboration will focus on integrating Ayar Labs’ technology to develop scale-out architectures enabled by high-bandwidth, low-latency and ultra-low-power optical-based interconnects for future NVIDIA products.
Ayar Labs has been working with GlobalFoundries (GF) since 2015 to develop and prove the GF Fotonix silicon photonics platform—from incorporating our PDK requirements and process optimizations to demonstrating the first working silicon on the platform. This cost-effective, high-volume process is geared for optical and optimized for monolithic design.
In March 2022, Ayar Labs and Lumentum announced a strategic collaboration agreement to deliver CW-WDM MSA-compliant external laser sources in high volume. Lumentum designs and manufactures innovative optical and photonic products and is a promoter-level member of the CW-WDM MSA.
MACOM designs and manufactures high-performance semiconductor products for the telecommunications, industrial, defense, and data center industries. MACOM is a promoter-level member of the CW-WDM MSA.
In September 2021, Ayar Labs and Sivers Photonics announced their partnership. Sivers develops CW-WDM MSA-compliant eight-wavelength distributed feedback (DFB) laser arrays for Ayar Labs' optical I/O solution. Sivers is a founding and promoter member of the CW-WDM MSA.
The CW-WDM MSA was formed to standardize WDM CW sources in O-band for emerging advanced integrated optics applications that are expected to move to 8, 16, and 32 wavelengths. These higher wavelength counts are needed for applications such as AI, HPC, and high-density optics, and enable a leap in performance, efficiency, cost, and bandwidth scaling compared with other technologies. The SuperNova™ multiwavelength optical source is the first product compliant with the optical source specifications of the CW-WDM MSA. Ayar Labs is a co-founder and promoter member of the CW-WDM MSA.
CXL is an industry consortium specification designed to enable any-to-any connectivity in high-performance datacenter computing. The consortium is an open interconnect CPU-to-device and CPU-to-memory ecosystem designed to remove the bottlenecks between general-purpose and accelerated processing architectures. Ayar Labs is an adopter member of CXL.
The UCIe standard is a new die-to-die interconnect standard for high-bandwidth, low latency, power-efficient, and cost-effective connectivity between chiplets. It is also the first specification to include an interface that is compatible with optical links. Ayar Labs produced the first optical I/O chiplet for the UCIe standard. It is a WDM optical chiplet using the AIB electrical interface, which is part of the UCIe standard. Ayar Labs is a contributing member of UCIe.