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2024 VLSI Symposium

June 16 @ 8:00 am - June 20 @ 5:00 pm HST

2024 IEEE Symposium on VLSI Technology & Circuits
June 16 – 20, 2024
Now in its 44th year of delivering a unique convergence of technology and circuits for the microelectronics industry, the 2024 IEEE Symposium on VLSI Technology & Circuits will feature selected presentations and panel sessions as well as advanced VLSI technology developments, innovative circuit designs, and the applications they enable, such as artificial intelligence, machine learning, IoT, wearable/implantable biomedical applications, big data, cloud/edge computing, virtual reality (VR)/augmented reality (AR), robotics, and autonomous vehicles.

2024 VLSI Symposium Program
2024 VLSI Symposium Registration

Ayar Labs at the 2024 VLSI Symposium

A 256 Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets
Pavan Bhargava, Director of Analog and Mixed Signal Design, Ayar Labs

We present a 256 Gbps WDM transceiver macro for use in co-packaged AI scale-out interconnects. The macro adopts an 8 λ × 32 Gbps configuration to achieve 256 Gbps per fiber. The transceiver macro operates error-free across a dynamic temperature ramp of 50-110° C, has >4 dB optical link margin with 4 dBm/𝜆 input laser power, and consumes 3.45 pJ/b (TX+RX). All transmit, receive, thermal control, and optical components are monolithically integrated in a 45 nm SOI process. An optical I/O chiplet with 8 WDM transceiver macros achieves <10-15 BER without FEC across 90 hours of operation in a 4 Tbps duplex link configuration.


June 16 @ 8:00 am HST
June 20 @ 5:00 pm HST


Hilton Hawaiian Village Waikiki Beach Resort
2005 Kālia Rd
Honolulu, HI 96815 United States
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