March 18-21, 2024, Charleston, SC
The GOMACTech conference was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for government reviews.
Ayar Labs at GOMACTech
GOMACTech Panel Discussions and Presentations
Session 36: Co-Packaged Analog-Drive High-Bandwidth Optical Input/Output (KANAGAWA)
You can see all Session 36 presentations by going to the GOMACTech Program page, then select the “2024 Preliminary Program” button (upper left). On this secondary Program page select Session 36 from the pulldown and hit Go.
TA6 — Photonic Technologies, Components, and Systems
Thursday, March 21
8:20 – 10:00 AM
Co-Chair: Dmitry Kozak
Naval Surface Warfare Center — Crane Division
36.2: Optical Assembly Challenges and Opportunities in Silicon Photonics Optical I/O Chiplets
Speaker: Chong Zhang, Director, Packaging Engineering, Ayar Labs
Co-Authors: Nhat Nguyen, Soumen Karmakar, Bob Paddison, Steve McGowan, Chen Sun, and Mark Wade, Ayar Labs
This paper explores packaging technologies for silicon photonics chiplets, underscoring the crucial role of in-package optical I/O chiplets in contemporary computing systems. The discussion covers considerations for first-level optical interfaces, and alongside a broader exploration of key criteria for materials and equipment in the optical assembly process.
36.3: Advancements in Co-Packaged Optics Technology: Integrated Optical I/O and FPGAs for New Platform Architectures
Speakers: John Oh, Allen Chan, Sergey Shumarayev, Saikumar Jayaraman, and Kumar Abhishek Singh, Intel Corporation
Co-Authors: Vladimir Stojanovic and Mark Wade, Ayar Labs
This paper describes the advancements made in heterogeneous MCP integration of electronic and photonic chiplets for co-packaged optical (CPO) technologies, the fiber attach process, and a demonstration vehicle for an optical FPGA compute platform, capable of 8 Tbps total Tx+Rx bandwidth with 10ns+ time of flight (ToF) link latency at 4-5 pJ/bit. This results in greater than 10x reduction in latency, 5x reduction in I/O power and 10x increase in face plate bandwidth density. This enables physical disaggregation of monolithic compute, communication, and sensing (radar) platforms, and drives new system architectures and capabilities.
Dig Deeper into Optical I/O
Optical I/O: Designing the Future of Digital Beamforming and Antenna Arrays
Phased array radar demands increasingly higher fidelity, which requires more elements generating more data. Only optical I/O from Ayar Labs provides the bandwidth density needed to deliver precise, higher fidelity phased array radar.
Enabling Data-Intensive, Real-Time Battlefield Communication: The Role of Silicon Photonics in Next-Gen Converged Sensor Platforms
This white paper explores the concept of “converged-aperture system architectures” and optical I/O’s role in moving data in next-generation interconnected battlefield systems.
Ayar Labs Optical I/O: Shattering the Barriers to AI at Scale
Generative AI model complexity is growing exponentially. Traditional interconnects create a bottleneck for data transfer, forcing GPUs to remain idle. Optical I/O connects nodes at scale so they work like one giant GPU.