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WEBINAR:

Meeting the Bandwidth Demands of Next-Gen HPC & AI System Architectures

In artificial intelligence (AI), increasingly complex algorithms, larger datasets, and process-intensive workloads lend to an insatiable demand for compute, memory, and storage, as well as higher-bandwidth, lower-latency communication between these components. Conversational AI, recommender systems, and computer vision are becoming increasingly prevalent, with new system architectures being explored to enable AI models with hundreds of trillions of parameters, and power supercomputers beyond exascale. These advances are bringing new challenges as the physical limitations of standard electrical interconnects are nearing the point of diminishing returns. Performance and efficiency losses from memory capacity limitations, network bottlenecks and stranded resources are being amplified at scale, creating a need for new system architectures to handle ever-growing, performance-intensive workloads.

In this panel discussion, we will hear from leading experts exploring innovative system designs and solutions for AI/HPC to address these challenges and unlock greater value from research, science, and business initiatives. Join this webinar to explore what these pioneers are learning as they define and develop new architectures and drive computing to the next level of performance.

Ayar Labs
US Department of Energy
Liqid
NVIDIA

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Speakers

Nicole Hemsoth

Moderator: Nicole Hemsoth

Deputy Editor in Chief, Situation Publishing & Co-Founder, The Next Platform

Nicole Hemsoth brings insight from the world of high performance computing following most recently a career covering supercomputing hardware and software as former Editor in Chief of long-standing supercomputing magazine, HPCwire. She was founding editor and conceptual creator of the data-intensive computing magazine Datanami, as well as the conceptual creator and founding Senior Editor for the large-scale infrastructure focused EnterpriseTech.

Vladimir Stojanovic

Vladimir Stojanovic

Co-Founder and Chief Architect at Ayar Labs

Vladimir Stojanovic is the Chief Architect of Ayar Labs. Prior to founding Ayar Labs, he led the team that designed the world’s first processor to communicate using light. Vladimir is also a Professor of EECS at UC Berkeley, and was one of the key developers of the Rambus high-speed link technology. He holds a PhD from Stanford University.

Christopher Long

Christopher Long

Chief Architect, Liqid

Chris is responsible for architecting cutting-edge enterprise class storage appliances & composable infrastructures, all phases of hardware & firmware design and development, and technically leadership. Bringing over 26 years of experience innovating groundbreaking hardware & firmware as a key contributor, lead, and principal engineer for companies like Seagate, SCI-Sanmina/Newisys, and L3 Communications. Chris has a broad knowledge of the computing and storage industry.

Si Hammond

Simon (Si) Hammond

Federal Program Manager, National Nuclear Security Administration (NNSA)

Si Hammond has worked on high-performance computing systems for over fifteen years, beginning his career at the University of Warwick and the UK’s AWE designing systems for physics simulations. In 2011, he moved to Sandia National Laboratories where he worked on the first Exascale codesign centers with the goal of delivering more than a thousand times increase in application performance. Currently, Si deploys world-leading HPC systems and supports application design to service every aspect of the NNSA’s stockpile stewardship mission.

Alex Ishii

Alex Ishii

Distinguished Architect, NVIDIA

Alex Ishii is a distinguished architect at NVIDIA, and has spent the last 8 years taking NVSwitch and NVLink-Network concepts from NVIDIA Research and shepherding them into cornerstones of some of the most advanced NVIDIA computing platforms. He holds a Ph.D. from MIT in Electrical Engineering and Computer Science, and has worked in areas as diverse as algorithm combinatorics, EDA tooling, metro-area switch architecture, and ultra-low-power clock distribution.

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