On the Winding Road through the Dolomites, Detroit, and DC

by | Aug 18, 2019

It feels like just yesterday that I wrote my last blog post — my, how time flies! ISC’19 was of course a great chance to reconnect with old partners and friends in the HPC community, but it was also an opportunity to collect first-hand feedback and requirements from all the major chip vendors and OEMs. No surprise, system and memory I/O bottlenecks are still an issue limiting supercomputer scalability.

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Bill Mannel, VP and GM of HPC at HPE, speaks to the deluge of data and compute’s struggle to keep up

Now, normally I’d expect a slow down in travel during the summer months, but this is startup (there are some great related memes online; I like the Spartan one)! Next up was a trip to Detroit for the annual DARPA ERI (Electronics Resurgence Initiative) Summit where Mark Wade presented a poster on our work to integrate the wide parallel AIB electrical I/O interface directly onto our TeraPHY chiplet (more details on the Advanced Interconnect Bus can be found here). In addition, we got great shout outs from our partners at Intel and GlobalFoundries about the work we’re doing together. The three key themes that kept coming up over and over again were:

1. Moore’s Law is slowing down and, without intervention, the electronics industry will struggle,

2. Chiplets are key to continue driving functionality and performance in-package,

3. Optical I/O is critical to scaling performance and capability.

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Intel Sr. PE Sergey Shumarayev explaining how Ayar Labs’ technology delivers 3 orders of magnitude improvement in I/O performance

Two weeks later, we were back in Washington, DC and shoulder to shoulder with industry leaders from AMD, Argonne, Cray, HPE, IBM, Intel, and others at the NITRD (Networking and Information Technology Research and Development Program)Future Computing Community Interest meeting. The meeting centered on exploring the “computing landscape for the coming decade and beyond, along with emerging and future application drivers, to inform agencies and to identify potential opportunities as well as gaps.” Once again, there was quite a bit of talk on the need to shore up Moore’s Law with chiplets and optical I/O.

And now for the short flight/drive up the road to Palo Alto… This week, we’re excited to be giving our first talk at HotChips, one of the industry’s premier semiconductor events! It’s a great honor for a startup to be invited and a validation of the technical direction and approach we’re taking for our products. I won’t steal Mark’s thunder, so if you’re at HotChips, please join us on Tuesday August 20th at 3:15pm for some exciting developments that we’ll talk about in conjunction with our partners at Intel. If you can’t make it in person, Mark will also be publishing a blog detailing the talk shortly thereafter.

Oh… and in case you were wondering about the Dolomites reference… a huge shout out to my good friend Gabriele Paciucci from Cray for planning the 3rd annual HPC motorcycle ride!

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Navigating the peaks and valleys of Northern Italy with some of HPC’s finest!

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