Enabling the next phase of Moore’s Law through optical connectivity

Ayar Labs solves the I/O bandwidth and power bottlenecks by moving data using light.

Come visit us at SC19!

Dramatically improving I/O performance at lower power

Enabling new system architectures and topologies

Improving resiliency and reach

Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by delivering a 1000x improvement in interconnect bandwidth density at 10x lower power. We use standard CMOS processing to develop high-speed, high-density, low-power optical interconnect “chiplets” and lasers to replace traditional electrical I/O.

Technical Brief: Optical I/O Chiplets Eliminate Bottlenecks to Unleash Innovation

This technical brief examines the evolution of optical communications in computing systems and the transition to ‘Phase Two’ of Moore’s Law through monolithic in-package optical I/O (MIPO I/O).

Download this technical brief to learn how Ayar Labs TeraPHY™ MIPO I/O Chiplets are enabling better bandwidth and better latency chip to chip communications at lower power.

Miss us at Hot Chips 2019?

President, Chief Scientist, and Co-Founder, Mark Wade presented Ayar Labs’ mission, product strategy, and collaboration with Intel. 

Intel and Ayar Labs demonstrated the industry’s first integration of monolithic in-package optics (MIPO) with a high-performance system-on-chip (SOC) co-packaged with the Intel Stratix 10 FPGA.

The Latest on Ayar Labs

Ayar Labs Realizes In-Package Optics

The holy grail of monolithic silicon photonics remains over the horizon, but photonic chiplets will enable leading-edge digital SoCs with in-package optics. In a segment littered with failed startups, Ayar Labs hopes to commercialize in-package optics using silicon...

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At Hot Chips, Intel Pushes ‘AI Everywhere’

What’s New: At Hot Chips 2019, Intel revealed new details of upcoming high-performance artificial intelligence (AI) accelerators: Intel® Nervana™ neural network processors, with the NNP-T for training and the NNP-I for inference. Intel engineers also presented...

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