Panel Discussion: Enabling HPC/AI Disaggregated System Architectures with Optical I/O
Disaggregated architectures decoupling memory from processors and accelerators allow for more flexible and cost-effective node designs that can meet the demands of next-generation HPC and AI workloads. For disaggregation to be possible, an I/O interconnect technology that can deliver high bandwidth throughput at low power and low latency over a relatively long distance of a few meters to 100s of meters is critically needed. Compute Express Link (CXL), an emerging unified protocol for disaggregated systems, uses PCIe electrical signaling for I/O interconnect which has limited reach. To extend the reach and fanout, there is strong interest for a “CXL over Optical” I/O interconnect. What optical I/O technology is best suited for this? In this panel discussion, we hear from experts who are building and exploring disaggregated architectures and are wrestling with the challenges of I/O interconnects.
- Timothy Prickett Morgan, (Moderator) Co-Editor, Co-Founder, The Next Platform
- Mike Ignatowski, Senior Fellow, AMD
- Hugo Saleh, VP of Marketing & Business Development, Ayar Labs
- Dr. Ian Karlin, Principal HPC Strategist, Lawrence Livermore National Laboratory
- Craig Prunty, VP of Marketing, SiPearl
- Mark Parsons, Director, EPCC, The University of Edinburgh