Webinar: Advanced Memory Architectures to Overcome Bandwidth Bottlenecks for the Exascale Era of Computing
A key barrier to unlocking future system performance is overcoming the bandwidth bottlenecks that limit inter-processor and memory performance. Current solutions, such as HBM and DDR5, are constrained because of thermal and signal integrity issues. New HPC and AI system architectures that decouple resources, such as CPUs, GPUs, FPGAs, and accelerators, could be the answer to some of the big memory challenges.
Central to enabling these new flexible system architectures will be high-bandwidth, low-latency optical interconnects. In this webinar, we’ll walk through examples of potential new architectures, technologies needed to enable them, and the ecosystem required to make them a reality.
- Addison Snell, (Moderator) CEO at Intersect360 Research
- Mohamad El-Batal, Chief Technologist for Cloud Systems at Seagate Technology
- Ivy Peng, Computer Scientist at Lawrence Livermore National Laboratory
- William Magro, Chief Technologist, High-Performance Computing at Google
- Dr. Vladimir Stojanovic, Chief Architect at Ayar Labs
- Marten Terpstra, Sr Director, PLM & Biz Dev, High Performance Networking and Silicon Photonics at HPE