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Discover how our optical I/O solution will solve the critical computing challenges of efficiency, density, and distance for next-gen system architectures.
This technical brief examines the evolution of optical communications in computing systems and the transition to ‘Phase Two’ of Moore’s Law through monolithic in-package optical I/O (MIPO I/O). Trends Driving Monolithic In-Package Optical Input/Output Chiplets...
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Abstract: This slide deck was presented by Mark Wade on August 20, 2019. (48 slides) Authors: Ayar Labs - Dr. Mark Wade, Erik Anderson, Dr. Shahab Ardalan, Pavan Bhargava, Sidney Buchbinder, Dr. Michael Davenport, Dr. John Fini, Dr. Anatoly Khilo, Roy Meade, Dr....
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.