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TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O
Abstract: This slide deck was presented by Mark Wade on August 20, 2019. (48 slides) Authors: Ayar Labs - Dr. Mark Wade, Erik Anderson, Dr. Shahab Ardalan, Pavan Bhargava, Sidney Buchbinder, Dr. Michael Davenport, Dr. John Fini, Dr. Anatoly Khilo, Roy Meade, Dr....
TeraPHY: A High-density Electronic-Photonic Chiplet for Optical I/O from a Multi-Chip Module
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS.
A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS
The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O.
WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers
In this work, we present WaveLight, a monolithic silicon-photonics platform whereby a low latency reliable deterministic protocol with optical functions are designed directly into an existing high-volume CMOS process.
Ultra-Efficient CMOS Fiber-to-Chip Grating Couplers
Apodized bi-level fiber-to-chip grating couplers, designed using a complex-wavevector band-structure approach, are demonstrated in a commercially available, monolithic SOI CMOS process achieving 92% (−0.36dB) coupling efficiency.
