Resources
We demonstrate 128 Gbps/port (8-λ×16 Gbps/λ) natively error-free transmission across eight optical ports using a ...
Ayar Labs’ in-package optical I/O solution includes the TeraPHY™ optical I/O chiplet and the SuperNova™ ...
Our longstanding relationship with DARPA has helped us to achieve a first-of-its-kind demonstration where we have ...
Abstract:
We demonstrate an electro-optic system enabling a direct optical I/O interface in an ASIC package. The ...
Abstract:
This slide deck was presented by Mark Wade on August 20, 2019. It explores Ayar Labs' innovative ...
In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.
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