WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation of Disaggregated Cloud Data Centers
In this work, we present WaveLight, a monolithic silicon-photonics platform whereby a low latency reliable deterministic protocol with optical functions are designed directly into an existing high-volume CMOS process.
Apodized bi-level fiber-to-chip grating couplers, designed using a complex-wavevector band-structure approach, are demonstrated in a commercially available, monolithic SOI CMOS process achieving 92% (−0.36dB) coupling efficiency.
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning
Here, we present a bit-statistical tuner that decouples tracking of optical one and zero-levels to realize non-dc-balanced data transmission, an “eye-max”-locking controller, and self-heating cancellation without need for a high-speed sensing frontend.
This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Quantum-Correlated Photon Pairs Generated in a Commercial 45 nm Complementary Metal-Oxide Semiconductor Microelectronic Chip
This proof-of-principle device demonstrates the potential of commercial CMOS microelectronics as an advanced quantum photonics platform with the capability of large volumes and pristine process control, where state-of-the-art high-speed digital circuits could interact with quantum photonic circuits.
In this paper, we demonstrate a highly directional vertical grating coupler with > 70% chip-to-fiber coupling efficiency (CE) and a 78 nm 1- dB bandwidth fabricated in a 45 nm commercially available microelectronics SOI CMOS process.
A silicon-photonic link is monolithically-integrated in a bulk CMOS process for the first time.
Based on a novel, “spoked-ring” active microcavity, we demonstrate optical modulators in an unmodified 45nm SOI CMOS process at 5Gbps with <5fJ/bit energy consumption; and filters with record thermal tuning efficiency of 2µW/GHz.