We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The 5.5×8.9mm 2 chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and integrates high-speed digital/analog circuits, optical modulators, photodetectors, and waveguides. Transmitters and receivers demonstrate data-rates up to 25Gbps at 4.9pJ/bit (Tx+Rx) and <10 -12 BER error free operation. We show a 32-channel, 512Gbps aggregate (across 4 Tx ports) wavelength-division multiplexed (WDM) transmit demonstration from a TeraPHY chiplet, running at 16Gbps per wavelength and 8 simultaneous wavelengths per port.



Chen Sun, Daniel Jeong, Mason Zhang, Woorham Bae, Chong Zhang, Pavan Bhargava, Derek Van Orden, Shahab Ardalan, Chandarasekaran Ramamurthy, Erik Anderson, Austin Katzin, Haiwei Lu, Sidney Buchbinder, Behrooz Beheshtian, Anatoly Khilo, Michael Rust, Chen Li, Forrest Sedgwick, John Fini, Roy Meade, Vladimir Stojanović, Mark Wade

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