Advancing Chiplet Design: TeraPHY hits 100G/wavelength

by | Mar 2, 2019

When I started working on microring-based optical I/O in 2011 during my PhD, my team’s effort was considered a moonshot by most in the industry. We were the “crazy academics” with a contrarian vision to building communication fabrics that could scale to the tens of terabits/second bandwidths expected for future systems-on-chip (GPUs, CPUs, FPGAs, ASICs, …).

Flash forward to 2015, and we published the first ever microprocessor chip to have optical I/O on the same piece of silicon as the processor [Nature]. That demonstration answered many feasibility and chiplet design questions while asking several more. Can we increase performance to higher per wavelength data rates (25/50/100 Gbps)? Can the thermal and manufacturing challenges surrounding microrings truly be solved such that they are a reliable technology for I/O?

By early 2018, we answered several of these questions with two demonstrations: a multi-wavelength complete link transmitting RapidIO data [HOTI] and a live demonstration at OFC showing 16x25Gbps transmitters performing link initialization, stabilization, and operation [ECOC].

One of the final questions for many people was: can the technology scale to 50/100Gbps per wavelength? This is an important question to gauge how long-lived a roadmap based on this technology might be—is this a one generation technology or a multi-generation technology?

Last week at ISSCC, the Ayar Labs team demonstrated dynamically configurable transmitters showing 20–100Gbps per wavelength, for which we received a Technology Innovation Award. This demonstration closed the books on the question of 50/100Gbps per wavelength and sets the stage for a multi-generation roadmap with relevance to nearly every high-performance SoC being developed.

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Folks trying to get a peek at the demo

Of course, that’s not to say we are finished. Now that the core technology feasibility and performance scaling potential has been demonstrated, the next set of questions are related to productization… what is the long-term reliability? What is the business model? What is the cost at high volumes? At Ayar Labs, answering these questions is the focus of 2019 and 2020, and we are fortunate to have the help of several large strategic partners who recognize we are entering a new era of photonics being directly integrated into SoC packages creating a roadmap for high-bandwidth, low-power optical I/O.

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