Advanced Memory Architectures to Overcome Bandwidth Bottlenecks for the Exascale Era of Computing
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November 10, 2021
9:00 – 10:00 a.m. PT
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A key barrier to unlocking future system performance is overcoming the bandwidth bottlenecks that limit inter-processor and memory performance. Current solutions, such as HBM and DDR5, are constrained because of thermal and signal integrity issues. New HPC and AI system architectures that decouple resources, such as CPUs, GPUs, FPGAs, and accelerators, could be the answer to some of the big memory challenges. Central to enabling these new flexible system architectures will be high-bandwidth, low-latency optical interconnects. In this webinar, we’ll walk through examples of potential new architectures, technologies needed to enable them, and the ecosystem required to make them a reality.
Moderated by industry analyst and CEO of Intersect360 Research, Addison Snell, the panel will feature thought leaders from Ayar Labs, Google, HPE, Lawrence Livermore National Laboratory, and Seagate.
Register to watch this webinar and hear these leading industry experts discuss their insights on what the future has in store for advanced memory architectures, including the challenges and opportunities presented and exciting new solutions using silicon photonics.
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CTO of Cloud Systems at Seagate Technology
Mohamad El-Batal is the Seagate Enterprise Data Solutions (EDS) Chief Technologist. As part of the overall Seagate Office of the CTO team, he is responsible for shaping the Seagate EDS strategy and future storage product technology roadmap. Having worked at leading storage technology companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, and NetApp, Mohamad has 20+ year history of enterprise storage architecture experience and innovation. Mohamad holds 28-issued and 12-pending storage patents, covering: Silicon, HA, FW, SSD, and Systems design focus areas.
Computer Scientist at Lawrence Livermore National Laboratory
Dr. Ivy Peng is a Computer Scientist in the Center for Applied Scientific Computing (CASC) at Lawrence Livermore National Laboratory, USA. Her research interests revolve around high-performance computing, focusing on advanced architectures, memory technologies, and performance optimization. Her recent works on memory systems include system-level characterization that guides future system designs and software solutions for leveraging persistent memory, heterogenous memory, and near-memory computing to accelerate critical workloads.
Chief Technologist, High-Performance Computing at Google
Bill is the Chief Technologist, High-Performance Computing at Google and has a long history in HPC. He was the co-chair of the Technical Working Group, responsible for the technical definition and evolution of the InfiniBand specification and standard, and has over 20 years of HPC experience at Intel, InfiniBand, And Google.
Moderator: Addison Snell
CEO at Intersect360 Research
Addison Snell is a veteran of the High-Performance Computing industry and the co-founder and CEO of Intersect360 Research, now in its 15th year delivering forecasts and insights for high-performance markets.
Co-Founder and Chief Architect at Ayar Labs
Vladimir Stojanovic is the Chief Architect of Ayar Labs. Prior to founding Ayar Labs, he led the team that designed the world’s first processor to communicate using light. Vladimir is also a Professor of EECS at UC Berkeley, and was one of the key developers of the Rambus high-speed link technology. He holds a PhD from Stanford University.
Sr Director, PLM & Biz Dev, High Performance Networking and Silicon Photonics at HPE
Marten Terpstra is the Sr Director of Product Management for High-Performance Fabrics in HPE’s High-Performance Computing and Mission Critical Systems business unit. In this role, Marten leads a group of senior product managers and technologists responsible for network fabrics for HPC and AI solutions. His group is also responsible for the introduction of Silicon Photonics into the network and overall system fabrics.